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-- Company: 
-- Engineer: 
-- 
-- Create Date:    07:59:02 04/07/2011 
-- Design Name: 
-- Module Name:    control_box - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity control_box is
    Port ( SAMPLE_A : in  STD_LOGIC_VECTOR (15 downto 0);
			  SAMPLE_B : in  STD_LOGIC_VECTOR (15 downto 0);
			  GAIN_0 : in STD_LOGIC;
			  GAIN_1 : in STD_LOGIC;
			  GAIN_2 : in STD_LOGIC;
			  GAIN_3 : in STD_LOGIC; 
			  GAIN : out STD_LOGIC_VECTOR (7 downto 0);
			  LINE_1 : out STD_LOGIC_VECTOR (63 downto 0); 
			  LINE_2 : out STD_LOGIC_VECTOR (63 downto 0);
			  BLANK : out STD_LOGIC_VECTOR (15 downto 0);
			  LED_0 : out STD_LOGIC;
			  LED_1 : out STD_LOGIC;
			  LED_2 : out STD_LOGIC;
			  LED_3 : out STD_LOGIC);
end control_box;

architecture Behavioral of control_box is
begin
	LINE_1 <= X"000000000000" & SAMPLE_B (15 downto 0);
	LINE_2 <= X"000000000000" & SAMPLE_A (15 downto 0);	 
	GAIN <= GAIN_3 & GAIN_2 & GAIN_1 & GAIN_0 & GAIN_3 & GAIN_2 & GAIN_1 & GAIN_0;
	BLANK <= X"0000";
	LED_0 <= GAIN_0;
	LED_1 <= GAIN_1;
	LED_2 <= GAIN_2;
	LED_3 <= GAIN_3;
end Behavioral;